Verilog Interview Questions

1. What is the difference between Verilog and C language?

2. What are the different types of modellings present in Verilog? Which is preferred and why?

3. Explain ASIC Design Flow.

4. What is the difference between reg and wire?

5. What are the different ports present in Verilog?

Solution :  input,output and inout

6. What is the default data type of  ports?

Solution: wire

7. What are the rules to be followed while using assign Keyword?

8. Why it is illegal to use reg variable to the LHS side of assign statement.

9. Which logic is inferred for Assign statements.

Solution : Combinational logic

10. What is the difference between bit wise Operator and logical operator?