UVM Interview Questions

UVM Concepts

1. What is UVM? How is it different from System Verilog

UVM is abbreviated as universal verification methodology. It is not a language, it is a methodology. Whereas SV is class based verification language built on top of Verilog by adding some additional constructs such as class, constraints, mailbox etc., The rich set of functions in UVM library are developed using SV. UVM library brings the  much automation and re-usability to system verilog test bench.

2. What is the difference between new() and create()?

New() is a class constructor, belonging to system verilog. It is used create an instance(object) of a class.

Create() is a factory method. Create() can be used to create instances of components and objects in UVM, once the components and objects are registered to the factory. 

The advantage of create over new is, create facilitates instance overriding.