1. RTl code: 2:1 Mux
module mux_2x1(a,b,sel,y);
input a,
b
sel;
output y;
assign y = (~sel&a)|(sel&b);
endmodule
2. RTl code: 4:1 Mux
module mux_4x1(a,b,c,d,s1,s0,y);
input a,b,c,d,s1,s0;
output y;
assign y = (~s1&~s0&a) | (~s1&s0&b) | (s1&~s0&c)| (s1&s0&d);
endmodule
3. RTL Code: Half Adder
module half_adder(a,b,sum,carry);
input a,
b;
output sum,
carry;
assign sum = a ^ b;
assign carry = a & b;
endmodule
4. RTL Code: Half Subtracter
module half_subtractor( a,b,diff,borrow);
input a,b;
output diff,borrow;
assign diff = a^b;
assign borrow= ~a & b;
endmodule
5. RTl code: 2:4 Decoder
module decoder_2_4 (
d_in, // 2 bit binary input
d_out, // 4-bit out
enable // Enable for the decoder
);
input [1:0] d_in ;
input enable ;
output [3:0] d_out ;
assign d_out[0] = ~d_in[0] & ~d_in[1]; // minterm 0
assign d_out[1] = ~d_in[0] & d_in[1]; // minterm 1
assign d_out[2] = d_in[0] & ~d_in[1]; // minterm 2
assign d_out[3] = d_in[0] & d_in[1]; // minterm 3
endmodule
6. RTl code: 4:16 Decoder using assign logic
module decoder_2_4 (
d_in, // 2 bit binary input
d_out, // 4-bit out
enable // Enable for the decoder
);
input [3:0] d_in ;
input enable ;
output [15:0] d_out ;
assign d_out = (enable) ? (1 << binary_in) : 16'b0 ;
endmodule
************* Structural coding Style *********
1. Verilog code: 4:1 Mux using 2:1 Mux
// RTl code: 2:1 Mux
module mux_2x1(a,b,sel,out);
input a,b,sel;
output out;
assign out = sel ? a : b;
endmodule
// Top Module : 4:1 Mux
module mux_4x1(a,sel,mux_out);
input [3:0] a;
input [1:0] sel;
output out;
wire w1,w2;
mux_2x1 M1(a[1],a[0],sel[0],w1);
mux_2x1 M2(a[3],a[2],sel[0],w2);
mux_2x1 M3(w2,w1,sel[1],out);
endmodule
// Test Bench Code:
module Mux_4x1_tb();
reg [3:0] a;
reg [1:0] sel;
wire mux_out;
integer i;
// DUT instantiation
mux_4x1 DUT(a,sel,mux_out);
initial
begin
a = 4'b0;
sel = 2'b0;
end
initial
begin
for(i=0;i<64;i=i+1)
begin
{sel,a} = i;
#10;
end
end
initial
$monitor("Input a = %b, Output sel = %b",a,sel);
initial
#1000 $finish;
endmodule
2. Full Adder using Half adder
module half_adder(a,b,sum,carry);
input a,
b;
output sum,
carry;
assign sum = a ^ b;
assign carry = a & b;
endmodule
module full_adder(input a,b,c,
output sum,carry);
wire w1,w2,w3;
//Instantiate the Half-Adder
half_adder H1(a,b,w1,w2);
half_adder H2(w1,c,sum,w3);
// Instantiate the OR gate
or OR1(carry,w3,w2);
endmodule
// full_adder TB code using Task
module full_adder_tb();
reg a,b,c;
wire sum,carry;
integer i,j,k;
//instantiation of the module
full_adder DUT(a,b,c,sum,carry);
//initialization
task initialize;
begin
{a,b,c}=0;
end
endtask
//input values
task inputs;
begin
for (i=0;i<8;i=i+1)
begin {a,b,c}=i;
#10;
end
end
endtask
//calling of task from initial process
initial
begin
initialize;
inputs;
end
//terminal display
initial
begin
$display("***** full adder outputs *****");
$monitor("a=%b,b=%b,c=%b,sum=%b,carry=%b",a, b,c,sum,carry);
#80 $finish;
end
//Use this snippet to see the waveform (If you are running codes in edaplayground)
initial
begin
$dumpfile("dump.vcd");
$dumpvars(0,a,b,c,sum,carry);
$dumpflush;
end
endmodule
// 3. ripple carry adder
// Refer 2nd code for Full Adder
module ripple_carry(input [3:0]a,input [3:0]b,input c,
output [3:0]sum,output carry);
wire [2:0]w;
full_adder fa1(a[0],b[0],c,sum[0],w[0]);
full_adder fa2(a[1],b[1],w[0],sum[1],w[1]);
full_adder fa3(a[2],b[2],w[1],sum[2],w[2]);
full_adder fa4(a[3],b[3],w[2],sum[3],carry);
endmodule
// TB Code
module ripple_carry_adder_tb();
reg [3:0]a,b;
reg c;
wire [3:0]sum;
wire carry;
integer i,j,k;
//instantiation of the module
ripple_carry DUT(a,b,c,sum,carry);
//initialization
task initialize;
begin
{a,b,c}=0;
end
endtask
//Generate Stimulous
task inputs;
begin
for(i=0;i<16;i=i+1)
begin
a=i;
for(j=0;j<16;j=j+1)
begin
b=j;
for(k=0;k<2;k=k+1)
begin
c=k;
#1;
end
end
end
end
endtask
//calling of task
initial
begin
initialize;
inputs;
end
//terminal display
initial
begin
$monitor("a=%b,b=%b,c=%b,sum=%b,carry=%b",a,
b,c,sum,carry);
#800 $finish;
end
// 4. Implement the full adder using 2x1 muxes only.
// RTl code: 2:1 Mux
module mux_2x1(a,b,sel,out);
input a,b,sel;
output out;
assign out = sel ? a : b;
endmodule
module full_adder_using_mux(i,sum,carry);
input [2:0]i; //i[2]=a; i[1]=b; i[0]=c;
output sum, carry;
wire w1,w2,w3,w4,w5;
//Sum of Full adder using mux
mux21 m1(1'b1,1'b0, i[0], w1);
mux21 m2(i[0],w1, i[1], w2);
mux21 m3(w1, i[0], i[1], w3);
mux21 m4(w2, w3, i[2], sum);
//Carry of Full adder using mux
mux21 m5(1'b0, i[1], i[0], w4);
mux21 m6(i[0], 1'b1, i[1], w5);
mux21 m7(w4 , w5 , i[2], carry);
endmodule
// RTl code: priority_encoder
module priority_circuit(i,y,idle);
input [7:0] p;
output [7:0] y;
output idle;
assign idle = ~p[0] & ~p[1] & ~p[2] & ~p[3] & ~p[4] & ~p[5] & ~p[6] & ~p[7];
assign y[0] = p[0] & ~p[1] & ~p[2] & ~p[3] & ~p[4] & ~p[5] & ~p[6] & ~p[7];
assign y[1] = p[1] & ~p[2] & ~p[3] & ~p[4] & ~p[5] & ~p[6] & ~p[7];
assign y[2] = p[2] & ~p[3] & ~p[4] & ~p[5] & ~p[6] & ~p[7];
assign y[3] = p[3] & ~p[4] & ~p[5] & ~p[6] & ~p[7];
assign y[4] = p[4] & ~p[5] & ~p[6] & ~p[7];
assign y[5] = p[5] & ~p[6] & ~p[7];
assign y[6] = p[6] & ~p[7];
assign y[7] = p[7];
endmodule
module binary_encoder(d_in,out);
input [7:0] d_in;
output [2:0] out;
assign out[0] = (d_in[1]|d_in[3]|d_in[5]|d_in[7]);
assign out[1] = (d_in[2]|d_in[3]|d_in[6]|d_in[7]);
assign out[2] = (d_in[4]|d_in[5]|d_in[6]|d_in[7]);
endmodule
module priority_encoder(d_in,out,idle);
input [7:0]d_in;
output [2:0] out;
output idle;
wire [7:0] p_out;
priority_circuit PC(d_in,p_out, idle);
binary_encoder BE(p_out,out);
endmodule
